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This document provides information and requirements for a two-phase project on designing a MIPS processor using VHDL for a computer architecture course. Phase I involves implementing a register file and ALU in VHDL. Phase II involves connecting these components to design a simple pipelined MIPS CPU that can execute R-type, I-type, and J instructions and test it using a Fibonacci number program. Students will submit VHDL code, a report, and present their work to the TA. The project aims to illustrate basic c

Author

Mohamed Alaa

Language

EN