Can I read Automatic UVM TestBench Generator for VLSI on EtoBox?

Automatic UVM TestBench Generator for VLSI by secondline2line is a document available to read on EtoBox.

What is Automatic UVM TestBench Generator for VLSI about?

The document presents AUTG, an Automatic UVM-based TestBench Generator designed to enhance the efficiency of VLSI chip design verification by automating the TestBench creation process. AUTG utilizes a golden reference and the port list of the Design Under Test (DUT) to generate a complete UVM TestBench, improving verification productivity while minimizing time and resource expenditure. Experimental results indicate that AUTG successfully generates functional verification code that effectively identifies bug

Author

secondline2line

Language

EN