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This document presents a high-speed, low-power multiplier utilizing a Spurious Power Suppression Technique (SPST) to enhance performance in digital systems. The proposed model integrates an FL-Multiplier with a Sklansky Adder and employs a Partial Product Reduction Algorithm, aiming for efficiency in speed and area while maintaining compatibility with IEEE 754 and posit formats. The design demonstrates reduced power consumption and improved reliability compared to conventional multipliers.
- Author
- ecehod
- Language
- EN