About this document
HDL Design Flow with Xilinx Vivado by 036 PRANEETHA S S is a document available to read on EtoBox.
The document describes designing and simulating an adder circuit using Cadence. It includes the aim to design a 4-bit adder, shows the schematic diagram of the adder, and presents the output waveforms of the transient simulation. The result indicates that the 4-bit adder circuit was successfully designed and simulated using Cadence. Pre-lab and post-lab questions related to adder design and simulation are also included.
- Author
- 036 PRANEETHA S S
- Language
- EN