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Pre-silicon Noise to Timing Test Methodology by Tan, Fern Nee ;Chuah, Jia Yun is a scholarly article available to read on EtoBox.

What is Pre-silicon Noise to Timing Test Methodology about?

This document provides a new pre-silicon PDN design methodology which validates the performance of the circuit design before it is approved for fabrication. It combines Signal and Power Integrity performance trades off of the General Purpose IO buffer. As the GPIO is built with a brand new silicon process, the method helps to define a new power integrity specification using the combined Signal and Power Integrity method, calculating on timing margins allowable. Traditionally, the power integrity solution metric is vastly defined by a hand-waving of +/-10% of nominal voltage.

Author

Tan, Fern Nee ;Chuah, Jia Yun

Publisher

IEEE

Published

2020

Language

EN