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8086 Microprocessor Architecture Overview by Ashwin Gopinath is a document available to read on EtoBox.

The document describes the architecture of the 8086 microprocessor. It has a 16-bit data bus and 20-bit address bus. The CPU is divided into two units - BIU and EU. BIU handles physical address calculation and communication with external devices. EU contains the register set, ALU, decoding unit, and timing/control unit. Memory is segmented into 64KB logical segments. The 20-bit physical address is generated by combining the 16-bit segment address and 16-bit offset. The instruction set includes data transfer

Author

Ashwin Gopinath

Language

EN