About this document
RISC-V MMU and Address Translation Details by DuongDTran is a document available to read on EtoBox.
The document discusses the supervisor trap value (stval) register which stores information about exceptions, such as the faulting instruction bits for an illegal instruction exception. It also covers the supervisor address translation and protection (satp) register which controls supervisor-mode address translation and protection by holding the physical page number of the root page table and other fields.
- Author
- DuongDTran
- Language
- EN