About this scholarly article

2018 IEEE International Electron Devices Meeting (IEDM) - Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Reduced Vertical Nanowires Separation, New Work Function Metal Gate Solutions, and DC/AC Performance Optimization by Ritzenthaler, R.; Mertens, H.; Pena, V.; Santoro, G.; Chasin, A.; Kenis, K.; Devriendt, K.; Mannaert, G.; Dekkers, H.; Dangol, A.; Lin, Y.; Sun, S.; Chen, Z.; Kim, M.; Machillot, J.; Mitard, J.; Yoshida, N.; Kim, N.; Mocuta, D.; Horiguchi, N. is a scholarly article available to read on EtoBox.

Author

Ritzenthaler, R.; Mertens, H.; Pena, V.; Santoro, G.; Chasin, A.; Kenis, K.; Devriendt, K.; Mannaert, G.; Dekkers, H.; Dangol, A.; Lin, Y.; Sun, S.; Chen, Z.; Kim, M.; Machillot, J.; Mitard, J.; Yoshida, N.; Kim, N.; Mocuta, D.; Horiguchi, N.

Publisher

IEEE

Published

2018