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DFT Flow: RTL to ATPG Coverage Guide by Jayraj SONI is a document available to read on EtoBox.

What is DFT Flow: RTL to ATPG Coverage Guide about?

This report outlines a comprehensive Design-for-Testability (DFT) flow using Synopsys DC Shell and Siemens Tessent to enhance testability in digital VLSI designs. The process includes RTL synthesis, scan chain insertion, Design Rule Checks, and ATPG pattern generation, achieving high fault coverage and ensuring design integrity. Results indicate improved testability with a stuck-at fault coverage increase from 98% to 100% and minimal timing impact from scan insertion.

Author

Jayraj SONI

Language

EN