About this document
VLSA Delay Time Analysis by Process Corner by pooja112 is a document available to read on EtoBox.
The document shows graphs of how the Δ bit of VLSA affected sense delay time under fast (f), typical-typical (tt), and slow-slow (ss) process corners. Higher Δ bit values increased delay time, with the ss corner having the highest delay and f corner the lowest across all Δ bit levels tested from 0 to 0.9. A second graph shows similar results for the Δ bit of VLSA-I under the three process corners.
- Author
- pooja112
- Language
- EN