About this document
Register File Design in RISC Processor by Romaan Ali is a document available to read on EtoBox.
The document describes a student project to design and implement a 16-bit pipelined RISC processor. The project involved dividing the work into circuit design, implementation in Logisim, and testing. Key components designed include the register file, ALU, control unit, forwarding logic, and pipeline registers. The processor was tested by running instructions to calculate the sum of two arrays. Pipeline hazards were addressed through stalling. The project provides insights into how to develop a simple proces
- Author
- Romaan Ali
- Language
- EN