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What is FPGA-Based Scalable Encryption Algorithm about?

This document summarizes research on improving the performance of the Scalable Encryption Algorithm (SEA) using a field-programmable gate array (FPGA). SEA is designed for resource-constrained systems and allows flexibility in key, text, and word sizes. The research proposes a low-cost FPGA implementation of SEA to evaluate its performance. It shows SEA achieves throughput and area requirements comparable to other block ciphers. Related work on AES hardware implementations and using FPGAs for cryptographic

Author

9949409548

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EN