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What is VLSI Logic Simulation and Verification about?
This document discusses VLSI systems for parallel logic simulation. It presents a platform for efficiently simulating high-level specifications of systems written in RTL, C, or C++ languages in parallel. The experimental platform uses the Zybo heterogeneous board containing a Zynq SoC with dual ARM CPUs and programmable logic. Functional verification is done through simulation-based methodologies to uncover design errors by exercising the design model. Parallel simulation improves efficiency over sequential
- Author
- Priyadarsini Karthik
- Language
- EN