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When Spatial and Temporal Locality Collide: the Case of the Missing Cache Hits by Mattias De Wael; David Ungar; Tom Van Cutsem is a scholarly article available to read on EtoBox.

What is When Spatial and Temporal Locality Collide: the Case of the Missing Cache Hits about?

Even the simplest hardware, running the simplest programs, can behave in the strangest of ways. Tracking down the cause of a performance anomaly without the complete hardware reference of a processor is a prime example of blackbox architectural exploration. When doubling the work of a simple benchmark program, that was run on a single core of Tilera's TILEPro64 processor, did not double the number of consumed cycles, a mystery was unveiled. After ruling out different levels of optimization for the two programs, a cycleaccurate simulation attributed the sub-optimal performance to an abnormally high number of L1 data cache misses. Further investigation showed that the processor stalled on every Read-After-Write instruction sequence when the following two conditions were met: 1) there are 0 or 1 instructions between the write and the read instruction and 2) the read and the write instructions target distinct memory locations that share an L1 cache line. We call this performance pitfall a RAW hiccup. We describe two countermeasures, memory padding and the explicit introduction of pipeline bubbles, that sidestep the RAW hiccup. This experience paper serves as a useful troubleshooting gu

Author

Mattias De Wael; David Ungar; Tom Van Cutsem

Publisher

ACM

Published

2013

Language

EN