About this document
Applsci 15 05012 by bahidjaizem is a document available to read on EtoBox.
This paper presents a novel heterogeneous-based network intrusion detection system (IDS) that combines FPGA and CPU capabilities to achieve high throughput and detection accuracy in high-speed networks. The proposed system utilizes a five-tuple segmented matching architecture and a hardware compiler supporting over 10,000 detection rules, resulting in a throughput of 100 Gbps and over 97% detection accuracy while consuming only 33% of hardware resources. Experimental results indicate significant performance
- Author
- bahidjaizem
- Language
- EN