About this document

VLSI Design Laboratory Manual by Sathya Vignesh is a document available to read on EtoBox.

This document describes the objectives and list of experiments for the VLSI Design Laboratory course EC6612. The objectives are to learn hardware description languages like Verilog and VHDL, fundamental principles of VLSI circuit design in digital and analog domains, and hands-on design experience using EDA tools. The list of experiments includes FPGA-based experiments involving HDL design, simulation, synthesis, mapping, and testing of modules like counters and adders. It also includes IC design experiment

Author

Sathya Vignesh

Language

EN