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Can I read Novel design of multiplier-less FFT processors on EtoBox?
Novel design of multiplier-less FFT processors by Yuan Zhou; J.M. Noras; S.J. Shepherd is a Computer Science article available to read on EtoBox.
What is Novel design of multiplier-less FFT processors about?
This paper presents a novel and hardware-efficient architecture for power-of-two FFT processors. The proposed design is based on the phase-amplitude splitting technique which converts a DFT to cyclic convolutions and additions. The cyclic convolutions are implemented with a filter-like structure and the additions are computed with several stages of butterfly processing units. The proposed architecture requires no multiplier, and comparisons with other designs show it can save up to 39% total equivalent gates for an 8-bit 16-point FPGA-based FFT processor.
Who reads Novel design of multiplier-less FFT processors?
It is typically read by researchers, students, and practitioners in Computer Science.
- Author
- Yuan Zhou; J.M. Noras; S.J. Shepherd
- Publisher
- Elsevier Science; Elsevier ; Elsevier BV (ISSN 0165-1684)
- Published
- 2007
- Language
- EN
- Field
- Computer Science (Physical Sciences)