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This paper presents a low power 10-bit 8-MS/s asynchronous SAR ADC with an on-chip reference voltage generator, achieving an effective number of bits (ENOB) of 9.56 and a signal-to-noise and distortion ratio (SNDR) of 59.3 dB while consuming only 572 µW of power. The design incorporates an inverted common-mode charge recovery technique to enhance linearity and reduce switching energy, alongside a rail-to-rail dynamic latch comparator with adaptive power control for improved efficiency. The architecture is r

Author

s-mo.abdallah

Language

EN