About this document
Multi-Input NAND Gate Design Lab by Shazid is a document available to read on EtoBox.
The document describes an experiment to design a multi-input NAND gate using PSPICE. The objectives are to: 1) Create the netlist of a 2-input NAND gate using CMOS logic. 2) Check the functionality and measure the rise/fall time. 3) Realize the effect of aspect ratios on rise/fall time. The document includes the PSPICE netlist for a 2-input NAND gate, and instructs students to write a netlist for a 3-input gate, simulate it, and discuss how aspect ratios affect timing.
- Author
- Shazid
- Language
- EN