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SRAM Write-Ability Enhancement Technique by Phoneix King is a document available to read on EtoBox.
This paper presents a technique to improve the write-ability of SRAM cells in deep sub-100 nm CMOS technology by using a transient negative bit-line voltage during write operations. The proposed method, which utilizes capacitive coupling to generate a negative voltage without requiring an external source, significantly reduces write failure probability by 103 times in simulations. The approach maintains column-based control to avoid read disturb failures while enhancing access transistor strength, thus impr
- Author
- Phoneix King
- Language
- EN